A 5-mW 0.26-mm2 10-bit 20-MS/s pipelined CMOS ADC with multi-stage amplifier sharing technique

被引：0

作者：

Jeon, Young-Deuk ^{[1
]}

Lee, Seung-Chul ^{[1
]}

Kim, Kwi-Dong ^{[1
]}

Kwon, Jong-Kee ^{[1
]}

Kim, Jongdae ^{[1
]}

Park, Dongsoo ^{[2
]}

机构：

[1] Electronics and Telecommunications Research Institute, Yuseong-Gu, Daejeon, 305-700, Korea, Republic of

[2] SIC Circuit Design Group, LG Electronics, Yeoksam-dong, Gangnam-gu, Seoul, 135-985, Korea, Republic of

来源：

ESSCIRC Proc. Eur. Solid State Circuits Conf. | 1600年 / 544-547期

关键词：

Compendex;

D O I：

ESSCIRC 2006 - 32nd European Solid-State Circuits Conference

中图分类号：

学科分类号：

摘要：

Amplifiers (electronic) - CMOS integrated circuits - Electric power utilization - Resistors - Signal distortion - Signal to noise ratio

引用