Design of FPGA Based Convolutional Neural Network Co-Processor

In the era of big data, the demand for computing resources and memory bandwidth in deep-level and large-scale deep learning network models is increasing exponentially. Traditional industry solution CPU+GPU is not suitable to the prevalent scenarios of mobile embedded applications. To deal with this problem, we proposed a design of convolutional neural network co-processor based on FPGA programmable logic device. This solution focuses on high compatibility. It has programmability and is compatible with a variety of network models to achieve hardware acceleration. It also has scalability to allow multi-core expansion within the range of hardware resources to achieve double performance. The design of convolutional operation module focuses on hardware parallelism and data reusability, which improves the utilization of hardware resources and computing efficiency. Rationally configured multi-level buffer structure reduces the co-processor's occupancy rate of external memory's read/write frequency and bandwidth, improves the internal communication efficiency of the module. The experimental results on the XILINX VC707 evaluation board show that the accuracy of the test set is 99%, the CIFAR-10 can achieve 80%, and the peak computing capability is 5.511×1010 s-1, the overall performance is approximately twice that of the general-purpose processor of Intel Xeno E5-2640 V4 server. Moreover, the processing performance of our design reaches the current mainstream level of FPGA solutions. © 2018, Editorial Office of Journal of Xi'an Jiaotong University. All right reserved.