Transmission Line Model testing of top-gate amorphous silicon thin film transistors

被引：0

作者：

Tosic, N. ^{[1
]}

Kuper, F.G. ^{[1
]}

Mouthaan, T. ^{[1
]}

机构：

[1] Univ of Twente, Enschede, Netherlands

来源：

Annual Proceedings - Reliability Physics (Symposium) | 2000年

关键词：

Amorphous silicon - Electric breakdown of solids - Electric discharges - Electrostatics - Failure analysis - Interfaces (computer) - Mathematical models - Semiconducting silicon - Semiconductor device testing - Threshold voltage - Transmission line theory;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

In this paper, for the first time Transmission Line Model (TLM) characterization is used to analyze ESD events in amorphous silicon thin film transistors (α-Si:H TFT). It will be shown that, above an ESD degradation threshold voltage, deterioration of electrical characteristics sets in, and that above another ESD failure threshold voltage, dielectric breakdown occurs. Electrical simulations of an α-Si:H TFT confirm creation of positive interface charges as being the most likely cause of the deterioration process. Two failure modes have been identified by failure analysis.

引用

页码：289 / 294