NCXplore: A design space exploration framework of temporal encoding for on-chip serial interconnects

被引:0
|
作者
Kornaros G. [1 ,2 ]
机构
[1] Electronics and Computer Engineering Department, Technical University of Crete, Kounoupidiana, Chania
[2] Applied Informatics and Multimedia Department, Technological Educational Institute of Crete, Heraklion, Crete
关键词
Bus encoding; Crosstalk; Design space exploration; On-chip interconnects; Power consumption; Switching activity;
D O I
10.1504/IJHPSA.2010.034539
中图分类号
学科分类号
摘要
Multi-processor systems-on-chip (MPSoC) seek for high performance, scalable and power efficient communication infrastructures. Recent research considers on-chip serial links for communication fabrics as a solution to reduce routing congestion and design complexity. This paper describes a methodology and a tool-chain for design space exploration of temporal encoding schemes, thereafter referred to as NCXplore. NCXplore assists the designer to achieve the best fit as regards both switching activity combined with reduction of crosstalk effects, and performance. A novel class of temporal encoding schemes is also presented to manage switching activity and crosstalk induced delays. NCXplore accepts any encoding technique as a mapping function to investigate crosstalk effects. Copyright © 2010 Inderscience Enterprises Ltd.
引用
收藏
页码:177 / 186
页数:9
相关论文
共 50 条
  • [1] Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures
    Malazgirt, Gorker Alp
    Yurdakul, Arda
    JOURNAL OF SYSTEMS ARCHITECTURE, 2017, 72 : 3 - 18
  • [2] A Design Space Exploration Method for on-Chip Memory System Based on Task Scheduling
    Meng, Hongyu
    Meng, Hongli
    Ding, Pengfei
    Wang, Mingxuan
    Wang, Donglin
    PROCEEDINGS OF 2018 IEEE 9TH INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING AND SERVICE SCIENCE (ICSESS), 2018, : 912 - 915
  • [3] A design methodology for efficient application-specific on-chip interconnects
    Ho, WH
    Pinkston, TM
    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2006, 17 (02) : 174 - 190
  • [4] Design automation for application-specific on-chip interconnects: A survey
    Cilardo, Alessandro
    Fusella, Edoardo
    INTEGRATION-THE VLSI JOURNAL, 2016, 52 : 102 - 121
  • [5] A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs
    Chariete, A.
    Bakhouya, M.
    Gaber, J.
    Wack, M.
    INTEGRATION-THE VLSI JOURNAL, 2015, 50 : 158 - 172
  • [6] Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture
    Lee, Jaekyu
    Li, Si
    Kim, Hyesoon
    Yalamanchili, Sudhakar
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 2013, 73 (12) : 1525 - 1538
  • [7] Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses
    Najeeb, K.
    Gupta, Vishal
    Kamakoti, V.
    Mutyam, Madhu
    JOURNAL OF LOW POWER ELECTRONICS, 2006, 2 (03) : 425 - 436
  • [8] Design Space Exploration of Nanoscale Interconnects with Rough Surfaces
    Kumar, Somesh
    Sharma, Rohit
    2015 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM, 2015, : 125 - 128
  • [9] Design and optimization of on-chip interconnects using wave-pipelined multiplexed routing
    Joshi, Ajay J.
    Lopez, Gerald G.
    Davis, Jeffrey A.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (09) : 990 - 1002
  • [10] Design of unidirectional emission silicon/III-V laser for on-chip interconnects
    Chucai Guo
    Yongzhen Huang
    Yuede Yang
    Xiaomeng Lv
    Qifeng Yao
    Frontiers of Optoelectronics, 2012, 5 (1) : 94 - 98