FPGA-based parallel access design for applications of voice signal processing

被引:1
作者
Zhu, Yong-Jin [1 ]
Cheng, You-Cai [1 ]
机构
[1] Electric and Electronic Department, Sichuan Vocational and Technical College
来源
Dianzi Keji Daxue Xuebao/Journal of the University of Electronic Science and Technology of China | 2012年 / 41卷 / 01期
关键词
Dynamic replacement; Field programmable gate array (FPGA); Parallel access; Voice signal processing;
D O I
10.3969/j.issn.1001-0548.2012.01.030
中图分类号
学科分类号
摘要
In order to realize real-time voice processing, a parallel access design based on FPGA is proposed. Low memory space is implemented by distributed CLBs while the high memory space is constructed by the embedded arrays on FPGA. The mapping from logical memory to physical memory is introduced. With the help of dynamical replacement algorithm, the frequently accessed memory block is mapped into low memory space. Our experiment results show that, the dynamic replacement algorithm keeps memory access performance in a suitable range.
引用
收藏
页码:158 / 160
页数:2
相关论文
共 10 条
  • [1] Tsai W.-T., Wei X., Paul R., Et al., Service-oriented system engineering (SOSE) and its applications to embedded system development, Service Oriented Computing and Applications, 1, 1, pp. 3-17, (2007)
  • [2] Petrov P., Orailoglu A., Dynamic tag reduction for low-power caches in embedded systems with virtual memory, International Journal of Parallel Programming, 35, 2, pp. 157-177, (2007)
  • [3] Chao Y.-B., Zhang X.-H., Speech recognition system on FPGA and Nios II softcore, Computer Engineering and Applications, 46, 2, (2010)
  • [4] Liu Y.-S., Huang X.-W., Zhao W.-Z., Application of multi-port memory in multicomputer system, Microcontrollers & Embedded Systems, 7, pp. 8-12, (2001)
  • [5] Virtex-II platform FPGAs complete data sheet, (2005)
  • [6] Mattausch H.J., Hierarchical N-port memory architecture based on 1-port memory cells, Solid-State Circuits Conference, 1997. ESSCIRC'97, Proceedings of the 23rd European, pp. 348-351, (1997)
  • [7] Wang Z., Gu Y.-J., A hierarchical architecture of N-port memory based on FPGA, International Conference on Convergence Information Technology, pp. 157-161, (2007)
  • [8] Virtex 2.5 V field programmable gate arrays, (2000)
  • [9] Gu Y.-J., Wang Z., Mapping N-port memory with dual-port array, World on Computer Science and Information Engineering, pp. 444-447, (2008)
  • [10] Mattausch H.J., Yamada K., Application of port-access-rejection probability theory for integrated N-port memory architecture optimization, Electronics Letters, 34, 9, pp. 861-862, (1998)