An automatic formal model generation and verification method for railway interlocking systems

被引：1
|
作者：
Oz, Muhammed Ali [1 ]
Kaymakci, Ozgur Turay [1 ]
机构：
[1] Department of Control and Automation Engineering, Faculty of Electrical and Electronics Engineering, Yildiz Technical University, Esenler, Istanbul, Turkey
来源：
Gazi University Journal of Science | 2017年 / 30卷 / 02期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Formal verification
引用
收藏
页码：133 / 147
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