Scaling Challenges for Advanced CMOS Devices

被引：78
作者：
Jacob A.P. [1 ]
Xie R. [1 ]
Sung M.G. [1 ]
Liebmann L. [1 ]
Lee R.T.P. [1 ]
Taylor B. [1 ]
机构：
[1] GLOBALFOUNDRIES, 400 Stonebreak Road ext., Malta, NY
来源：
Jacob, Ajey P. (ajey.jacob@globalfoundries.com) | 2017年 / World Scientific卷 / 26期
关键词：
10nm; 14nm; 22nm; 5nm; 7nm; BEOL; Bulk silicon; channel engineering; CMOS; contact engineering; contacted poly pitch or gate pitch (CPP); design technology co-optimization (DTCO); Epitaxial (epi); FDSOI; FEOL; fin; fin pitch; finFET; gate engineering; Germanium; III-V; Indium Gallium Arsenide (InGaAs); interconnect capacitance; interconnect patterning; technology node; interconnect resistance; Nanowire FET; replacement metal gate (RMG); Self-aligned contact (SAC); self-aligned double patterning (SADP); self-aligned quadruple patterning (SAQP); Silicon; Silicon Germanium (SiGe); single and double diffusion; SOI; source drain (S/D)engineering; source drain epi; Vertical FET;
D O I：
10.1142/S0129156417400018
中图分类号：
学科分类号：
摘要：
The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors. © 2017 World Scientific Publishing Company.
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