A new nanoscale DG MOSFET design with enhanced performance – a comparative study

被引：0
作者：
Mohapatra, Sushanta Kumar [1 ]
Pradhan, Kumar Prasannajit [1 ]
Sahu, Prasanna Kumar [1 ]
机构：
[1] Department of Electrical Engineering, National Institute of Technology, Rourkela, Odisha
来源：
Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, LNICST | 2014年 / 117卷
关键词：
ATLAS™ device simulator; DG; Gate Stack (GS) engineering; MOSFET; SCEs; Silicon-on-insulator (SOI); TM-DG;
D O I：
10.1007/978-3-319-11629-7_11
中图分类号：
学科分类号：
摘要：
Triple Material (TM) Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with high-k dielectric material as Gate Stack (GS) is presented in this paper. A lightly doped channel has been taken to enhance the device performance and reduce short channel effects (SCEs) such as drain induced barrier lowering (DIBL), sub threshold slope (SS), hot carrier effects (HCEs), channel length modulation (CLM). We investigated the parameters like Surface Potential, Electric field in the channel, SS, DIBL, Transconductance (gm) for TM-GS-DG and compared with Single Material (SM) DG and TM-DG. The simulation and parameter extraction have been done by using the commercially available device simulation software ATLAS™. © Institute for Computer Sciences, Social Informatics and Telecommunications Engineering 2014.
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页码：76 / 81
页数：5
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