Design of a Low Jitter Phase Locked Loop for Array TDC

被引：0

作者：

Wu J. ^{[1
]}

Sun Y.-W. ^{[1
]}

Peng J. ^{[1
]}

Zheng L.-X. ^{[1
]}

Luo M.-C. ^{[2
]}

Sun W.-F. ^{[1
]}

机构：

[1] Southeast University, Nanjing, 210096, Jiangsu

[2] 44th Research Institute of China Electronic Technology Group, Chongqing

来源：

Tien Tzu Hsueh Pao/Acta Electronica Sinica | 2020年 / 48卷 / 09期

关键词：

Low jitter; Phase locked loop; Phase noise;

D O I：

10.3969/j.issn.0372-2112.2020.09.006

中图分类号：

学科分类号：

摘要：

The traditional PLL(Phase Locked Loop) circuit is limited by the selection of loop parameters and its phase noise and jitter characteristics have been difficult to meet the application requirements of large array and high precision TDC(Time-to-Digital Converter). This paper devotes to the optimal selection of PLL loop bandwidth and a PLL circuit with low noise and low jitter characteristics is designed. The chip area is approximately 0.745mm×0.368mm. The actual test results of the chip show that under the condition of external signal source input 15.625MHz clock signal and the PLL output frequency can be locked at 250. 0007MHz. The frequency deviation is 0.7kHz. The duty cycle of the output clock is 51.59% and the phase noise is-114.66dBc/Hz@ 1MHz. The RMS jitter of the clock is 4.3ps and the peak-to-peak jitter is 32.2ps. The phase noise of the phase-locked loop is significantly reduced and the jitter characteristics of the output clock are significantly optimized, which can basically meet the application needs of the array TDC. © 2020, Chinese Institute of Electronics. All right reserved.

引用

页码：1703 / 1710

页数：7

共 12 条

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