Hardware countermeasure against side-channel attacks based on randomized instruction injection

被引:0
作者
He, Zhangqing [1 ,2 ]
Ao, Tianyong [1 ,3 ]
Liu, Kai [1 ]
Dai, Kui [1 ]
机构
[1] School of Optical and Electronic Information, Huazhong University of Science and Technology
[2] School of Electrical and Electronic Engineering, Hubei University of Technology
[3] School of Physics and Electronics, Henan University, Kaifeng 475004, Henan
来源
Huazhong Keji Daxue Xuebao (Ziran Kexue Ban)/Journal of Huazhong University of Science and Technology (Natural Science Edition) | 2014年 / 42卷 / 05期
关键词
Configuration register; Countermeasures; Random delays; Randomized instruction injection; Side channel attacks;
D O I
10.13245/j.hust.140526
中图分类号
学科分类号
摘要
A randomized instruction injection technique was proposed, and the instruction injection hardware module which could generate random instructions and insert them into the normal instruction streams at any time was integrated into CPU (central processing unit). The power profile of a cryptographic application will be confused by the module, leading to power analysis attacks becoming very hardly and even impossible. The shadow registers and other strategies were used to resolve the conflict between the execution of normal instructions and random instructions. A configuration register was used to control the operating modes and reduce the overhead of randomized instruction injection. Experimental results show that the countermeasure proposed has stronger security and lower cost than that of current techniques.
引用
收藏
页码:128 / 132
页数:4
相关论文
共 13 条
[1]  
Kocher P., Jaffe J., Jun B., Differential power analysis, 19th Annual International Cryptology Conference, pp. 388-397, (1999)
[2]  
Clavier C., Coron J., Dabbous N., Differential power analysis in the pres ence of hardware countermeasures, Workshop on Cryptographic Hardware and Embedded Systems 2000, pp. 252-263, (2000)
[3]  
Rovain M., Prouff E., Provably secure higher-order masking of AES, Workshop on Cryptographic Hardware and Embedded Systems 2010, pp. 413-427, (2010)
[4]  
Tiri K., Hwang D., Hodjat A., Et al., Prototype IC with WDDL and differential routing-DPA resistance assessment, Workshop on Cryptographic Hardware and Embedded Systems 2005, pp. 354-365, (2005)
[5]  
Kocher P., Jaffe J., Using unpredictable information to minimize leakage from smartcards and other cryptosystems
[6]  
May D., Muller H.L., Smart N.P., Non-deterministic processors, Information Security and Privacy, 2119, pp. 115-129, (2001)
[7]  
Akkar M.L., Bevan R., Dischamp P., Et al., Power analysis, what is now possibl e⋯, Proceedings of the 6th International Conference on the Theory and Appl ication of Cryptology and Information Security (ASIACRYPT'00), pp. 489-502, (2000)
[8]  
Charvillon N.V., Medwed M., Kerckhof S., Et al., Shuffling against side-chann el attacks a comprehensive study with cautionary note, The 18th Annual International Conference on the Theory and Application of Cryptology and Information Security., pp. 740-757, (2012)
[9]  
Coron J.S., Kizhvatov I., Analysis and improvement of the random delay countermeasure of CHES 2009, Workshop on Cryptographic Hardware and Embedded Systems 2010, pp. 95-109, (2010)
[10]  
Durvaux F., Renauld M., Standaert F.X., Et al., Efficient removal of random d elays from embedded software implementations using hidden Markov models, Sm art Card Research and Advanced Applications, 7771, pp. 123-140, (2013)