Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise

被引：0

作者：

Wang X. ^{[1
]}

Kennedy M.P. ^{[1
]}

机构：

[1] University College Dublin, School of Electrical and Electronic Engineering, Microelectronic Circuits Centre Ireland

来源：

IEEE Transactions on Circuits and Systems I: Regular Papers | 2023年 / 70卷 / 12期

基金：

爱尔兰科学基金会;

关键词：

Bang-bang; DCO; digital PLL; discrete-time; frequency synthesizer; jitter; jitter minimization; multi-rate; phase detector; phase noise; PLL; quantization error; TDC;

D O I：

10.1109/TCSI.2023.3305604

中图分类号：

学科分类号：

摘要：

Bang-bang digital phase locked loops (BBDPLL's) use a binary phase detector (BPD) to limit the complexity and consumption of area and power of the time-to-digital converter (TDC), which inevitably introduces more quantization errors (QE's) than a conventional high-resolution TDC. Coarse-resolution TDCs with a few more bits than the BPD can help to mitigate the TDC-induced output jitter and phase noise (PN). This paper derives estimates of the RMS input and output jitters of such digital phase locked loops (DPLL's) with mid-rise TDCs, including BBDPLLs, based on a multi-rate discrete-time model. A comprehensive jitter minimization strategy is provided. The impact of this type of jitter minimization on the enhancement of the output PN performance is studied for the first time. Behavioral simulations verify our analysis. Finally, we conclude with design rules of thumb and a design procedure that helps to mitigate the system jitter and to achieve an output PN spectrum that is dominated by the noises contributed by the reference and digitally controlled oscillator (DCO). © 2004-2012 IEEE.

引用

页码：5124 / 5137

页数：13

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