Modeling process variability in scaled CMOS technology

被引：75
|
作者：
Saha S.K. [1 ]
机构：
[1] University of Colorado, Colorado Springs
来源：
IEEE Design and Test of Computers | 2010年 / 27卷 / 02期
关键词：
Compact variability modeling; Design and test; Gate-oxide thickness variability; High-k dielectric; Line-edge roughness; Metal gate; Polysilicon granularity; Process variability; Random discrete dopants; Scaled CMOS technology; Statistical compact modeling;
D O I：
10.1109/MDT.2010.50
中图分类号：
学科分类号：
摘要：
Editor's note: Process variability has become a critical issue in scaled CMOS design. This article provides a comprehensive view on the predominant variation sources in sub-90-nm devices, their impact on device and circuit performance, and various modeling approaches for statistical circuit analysis. © 2010 IEEE.
引用
收藏
页码：8 / 16
页数：8
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