A low-cost compact AES architecture for wireless sensor network

The implementation of small size cryptography algorithm is a critical problem for wireless sensor network. A low cost compact intellectual property (IP) core of the entire advanced encryption standard (AES) algorithm for wireless sensor network is presented in this paper. A compact encryption and decryption system using only four sharing S-Boxes is obtained, employing sharing between the encryption and decryption processes. Our design proposes use of composite field data path for the SubBytes and In-vSubBytes transformations. With an implementation of the AES block cipher with Virtex II Pro FPGA using 0.13 μm and 90 nm process technology, our area optimized consumes 16.8k equivalent gates. The speed of this implementation is also reduced to 0.45 Gbits/s. Compared with previous implementations, our design achieves significant low-cost area with acceptable throughput. Copyright © by HIGN TECHNOLOGY LETTERS PRESS.