Transient characteristic analysis of a double-gate dual-strained-channel SOI CMOS

被引：0
|
作者：
Sun, Liwei [1 ]
Gao, Yong [1 ]
Yang, Yuan [1 ]
Liu, Jing [1 ]
机构：
[1] Department of Electronic Engineering, Xi'an University of Technology, Xi'an 710048, China
来源：
Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors | 2008年 / 29卷 / 08期
关键词：
Control mechanism - Conversion time - Double gate - Dual-strained-channel - Effective gate length - Novel structures - Strained SiGe - Transient characteristic;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：1566 / 1569
相关论文
共 50 条
  • [41] Strained-Si channel super-self-aligned back-gate/double-gate planar transistors
    Lin, Hao
    Liu, Haitao
    Kumar, Arvind
    Avci, Uygar
    Van Delden, Jay S.
    Tiwari, Sandip
    Kumar, Arvind
    IEEE ELECTRON DEVICE LETTERS, 2007, 28 (06) : 506 - 508
  • [42] The analog/RF performance of a strained-Si graded-channel dual-material double-gate MOSFET with interface charges
    Suddapalli, Subba Rao
    Nistala, Bheema Rao
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2021, 20 (01) : 492 - 502
  • [43] Transient analysis of 3.3kV double-side double-gate IGBTs
    Hobart, KD
    Kub, FJ
    Ancona, M
    Neilson, JM
    Waind, PR
    ISPSD '04: PROCEEDINGS OF THE 16TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS, 2004, : 273 - 276
  • [44] Optimization of parameters of double-gate sub-20 nanometers SOI CMOS transistors with architecture “without overlapping”
    N. V. Masalsky
    Russian Microelectronics, 2012, 41 (1) : 51 - 58
  • [45] Analytical threshold voltage model for short channel n(+)-p(+) double-gate SOI MOSFET's
    Suzuki, K
    Tosaka, Y
    Sugii, T
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (05) : 732 - 738
  • [46] Performance limitation of sub-100-nm intrinsic-channel double-gate SOI MOSFETs
    Omura, Y
    Yanagi, SI
    2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2002, : 60 - 61
  • [47] Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET
    Hosseini, Reza
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2016, 15 (03) : 787 - 794
  • [48] Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET
    Reza Hosseini
    Journal of Computational Electronics, 2016, 15 : 787 - 794
  • [49] Novel Technique Of Source And Drain Engineering For Dual-Material Double-Gate (DMDG) SOI MOSFETS
    Yadav, Himanshu
    Malviya, Abhishek Kumar
    Chauhan, R. K.
    INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, MATERIALS AND APPLIED SCIENCE, 2018, 1952
  • [50] Two-dimensional quantum-mechanical modeling for strained silicon channel of double-gate MOSFET
    Kim, K
    Kwon, O
    Seo, J
    Won, T
    Birner, S
    Oberhuber, R
    Trellakis, A
    JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 2004, 45 : S909 - S913
12345