FPGA implementation of high-throughput irregular structured LDPC encoder and decoder

被引:0
|
作者
Wang, Wenjun
Zhu, Xiaoxuan
Kang, Guixia
Zhang, Ping
机构
[1] Key Laboratory of Universal Wireless Communications (Ministry of Education), Beijing University of Posts and Telecommunications, Beijing 100876, China
[2] Wireless Technology Innovation Institute, Beijing University of Posts and Telecommunications, Beijing 100876, China
来源
Shuju Caiji Yu Chuli/Journal of Data Acquisition and Processing | 2008年 / 23卷 / SUPPL.期
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:113 / 118
相关论文
共 50 条
  • [21] New Memory Load Optimization Approach for Software Implementation of Irregular LDPC Encoder/Decoder
    Benhayoun, Mhammed
    Mansouri, Anas
    Razi, Mouhcine
    Ahaitouf, Ali
    2019 INTERNATIONAL CONFERENCE ON WIRELESS TECHNOLOGIES, EMBEDDED AND INTELLIGENT SYSTEMS (WITS), 2019,
  • [22] LDPC Decoder Implementation Using FPGA
    Kiaee, Mahdie
    Gharaee, Hossein
    Mohammadzadeh, Naser
    2016 8TH INTERNATIONAL SYMPOSIUM ON TELECOMMUNICATIONS (IST), 2016, : 167 - 173
  • [23] An FPGA implementation of array LDPC decoder
    Sha, Jin
    Gao, Minglun
    Zhang, Zhongjin
    Li, Li
    Wang, Zhongfeng
    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 1675 - +
  • [24] High-throughput LDPC decoder for long code-length
    Ishikawa, Tatsuyuki
    Shimizu, Kazunori
    Ikenaga, Takeshi
    Goto, Satoshi
    2006 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERS, 2006, : 101 - +
  • [25] VLSI Implementation of a High-Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes
    Cho, Junho
    Kim, Jonghong
    Sung, Wonyong
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (05) : 1083 - 1094
  • [26] High-throughput DOCSIS Upstream QC-LDPC Decoder
    Wu, Michael
    Yin, Bei
    Miller, Eric
    Dick, Chris
    Cavallaro, Joseph R.
    CONFERENCE RECORD OF THE 2014 FORTY-EIGHTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, 2014, : 537 - 541
  • [27] High Throughput GPU LDPC Encoder and Decoder for DVB-S2
    Kun, David
    2018 IEEE AEROSPACE CONFERENCE, 2018,
  • [28] Fully parallel FPGA decoder for irregular LDPC codes
    Broulim, Jan
    Broulim, Pavel
    Moldaschl, Jan
    Georgiev, Vjaceslav
    Salom, Radek
    2015 23RD TELECOMMUNICATIONS FORUM TELFOR (TELFOR), 2015, : 309 - 312
  • [29] FPGA Implementation of a Clockless Stochastic LDPC Decoder
    Ceroici, Chris
    Gaudet, Vincent C.
    PROCEEDINGS OF THE 2014 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS 2014), 2014, : 210 - 214
  • [30] Hardware implementation of the LDPC decoder in the FPGA structure
    Kuc, Mateusz
    Sulek, Wojciech
    Kania, Dariusz
    PRZEGLAD ELEKTROTECHNICZNY, 2019, 95 (03): : 58 - 62