Design and implementation of transmitter module in 40 Gbit/s very short reach optical transmission system

Stratix II GX FPGA from the Altera Corporation is employed to implement the transmitter module in a 40 Gbit/s very short reach optical transmission system. This paper focuses on the design of 16:12 converter. The high speed interface is designed based on the high speed transceiver: At the receiver, two methods are adopted to align the phase of the 17-channel data; at the transmitter, additional synchronization measure is taken to satisfy the demand from the clock management unit (CMU) to the data transmission between asynchronous clock domains, ensuring the stability of the transceiver. On these bases, the clock network is implemented by considering the reliability and the facility of the follow-up testing. Meantime, a frame aligner based on a synchronous digital hierarchy (SDH) structure, as well as the deskew circuit and the 16:12 mapping module is devised, achieving the conversion of data from SFI-5 interface to VSR-5 interface; the deskew module can eliminate the skew of 512 bits dynamically. The testing results using Signaltap II verify the validity of the design. Measured by the Agilent 81250, the error bit rates also meet the design index of being less than 10-12.