A SysML and CLEAN-based methodology for digital circuits design

The increasing complexity of electronic systems requires a powerful abstraction and structuration mechanisms, as well as design methodologies that systematically and formally derives low-level concrete designs from high-level abstract ones. For this reason, in this research work, we present a methodological design approach that automatically generates a functional HDL code from SysML diagrams modelling hardware design. The generated HDL code is both verifiable and executable. While the first feature remains crucial for low-level design refinements, the second one enables design performance evaluation at early stages. In order to shed light on the features of the proposed approach, a case study is given. Specifically, it involves designing the micro-architecture of MIPS processor, generating its functional specification in CLEAN from its SysML model, and simulating it. © 2016 Inderscience Enterprises Ltd.