A Low Cost Reconfigurable Architecture for a UMTS Receiver

被引：0

作者：

Veljanovski, Ronny ^{[1
]}

Stojcevski, Aleksandar ^{[1
]}

Singh, Jugdutt ^{[1
]}

Zayegh, Aladin ^{[1
]}

Faulkner, Michael ^{[1
]}

机构：

[1] School of Electrical Engineering, Victoria University of Technology, PO Box 14428, Melbourne City MC, Vic., Australia

来源：

| 2003年 / Institute of Electronics, Information and Communication, Engineers, IEICE卷 / E86-B期

关键词：

Computer simulation - Digital filters - Energy dissipation - Mobile telecommunication systems - Radio interference - Statistical methods - Synchronization - Telecommunication links;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A novel reconfigurable architecture has been proposed for a mobile terminal receiver that can drastically reduce power dissipation dependant on adjacent channel interference. The proposed design can automatically scale the number of filter coefficients and word length respectively by monitoring the in-band and out-of-band powers. The new architecture performance was evaluated in a simulation UTRA-TDD environment because of the large near far problem caused by adjacent channel interference from adjacent mobiles and base stations. The UTRA-TDD downlink mode was examined statistically and results show that the reconfigurable architectures can save an average of up to 75% power dissipation respectively when compared to a fixed filter length of 57 and word length of 16 bits. This power saving only applies to the filter and ADC, not the whole receiver. This will prolong talk and standby time in a mobile terminal. The average number of taps and bits were calculated to be 14.98 and 10 respectively, for an outage of 97%.

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