Formation and Metallization Process Study on High Aspect Ratio Through-Glass-Via (TGV) Within Photosensitive Glass

被引：0

作者：

Lin L.-C. ^{[1
]}

Wang Q.-D. ^{[1
]}

Qiu D.-L. ^{[1
]}

Wu H. ^{[2
]}

Xue K. ^{[2
]}

Yu D.-Q. ^{[2
]}

Cao L.-Q. ^{[1
]}

机构：

[1] Institute of Microelectronics of Chinese Academy of Sciences, Beijing

[2] National Center for Advanced Packaging, Wuxi, 241350, Jiangsu

来源：

| 2018年 / Beijing Institute of Technology卷 / 38期

关键词：

Current density; Filling process; Interposer technology; Photosensitive glass; Through glass via;

D O I：

10.15918/j.tbit1001-0645.2018.01.009

中图分类号：

学科分类号：

摘要：

The electromagnetic simulations of through glass via (TGV) and through silicon via (TSV) were performed in this paper. Simulated results show that the insertion losses of TGV and TSV at 20 GHz are -0.024 dB and -1.62 dB respectively, representing a much higher performance of TGV. Based on photosensitive glass, 7:1 high aspect ratio of TGV was obtained by using high speed wet etching method, achieving better array profile, uniformity and less 1 μm roughness of TGVs. Filling process was simulated under different current densities. Results show that smaller current density is helpful to achieve uniform filling due to the improvement of crowding effect of current density at the top and bottom of TGVs, the development speed of copper layer is more uniform and slow. A verification filling experiments were carried out under the current density of 1ASD. Results show a high filling quality, copper layer develops uniformly in 120 μm TGVs, the seams are small in 70 μm TGVs. © 2018, Editorial Department of Transaction of Beijing Institute of Technology. All right reserved.

引用

页码：52 / 57

页数：5

共 16 条

[1] Garrou P., Vitkavage S., Arkalgud S., Handbook of 3D Integration, (2007)
[2] Song C., Study on interconnect technology for three-dimensional integration, (2010)
[3] Joyner J.M., Zarkesh-Ha P., Meindl J.D., Global interconnectdesign in a three-dimensional system-on-a-chip, VLSI Systems, 4, pp. 367-372, (2004)
[4] Banijamali B., Ramalingam S., Nagarajan K., Et al., Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), pp. 285-290, (2011)
[5] Reum OH., Design technologies for a 1.2 V 2.4 Gb/s/pin high capacity DDR4 SDRAM with TSVs, 2014 Symposium on VLSI Circuits Digest of Technical Papers, pp. 1-2, (2014)
[6] Sukumaran V., Bandyopadhyay T., Sundaram V., Et al., Low-cost thin glass interposers as a superior alternative to silicon and organic interposers for packaging of 3-D ICs, IEEE Transactions on Components, Packaging and Manufacturing Technology, 2, 9, pp. 1426-1433, (2012)
[7] Sukumaran V., Design, fabrication, and characterization of ultrathin 3-D glass interposers with through-package-vias at same pitch as TSVs in silicon, IEEE Transactions on Components, Packaging and Manufacturing Technology, 4, 5, pp. 786-795, (2014)
[8] Huang T., Chou B., Sundaram V., Et al., Novel copper metallization schemes on ultra-thin, bare glass interposers with through-vias, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), pp. 1208-1212, (2015)
[9] Takahashi S., Horiuchi K., Tatsukoshi K., Et al., Development of through glass via (TGV) formation technology using electrical discharging for 2.5/3D integrated packaging, 2013 IEEE 63rd Electronic Components and Technology Conference, pp. 348-352, (2013)
[10] Yook J.M., Kim D., Kim J.C., High performance IPDs (Integrated passive devices) and TGV (Through glass via) interposer technology using the photosensitive glass, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), pp. 41-46, (2014)

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