Design and implementation of the FFT parallel processor based on ASIP

被引：0

作者：

Zhang L. ^{[1
]}

Li S.-F. ^{[1
]}

Shi G.-M. ^{[1
]}

Li F. ^{[1
]}

机构：

[1] School of Electronic Engineering, Xidian Univ.

来源：

Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University | 2010年 / 37卷 / 04期

关键词：

Application specific instruction set processor(ASIP); Data communication; Fast Fourier transform(FFT); Parallel processing; Reduced instruction set computer (RISC);

D O I：

10.3969/j.issn.1001-2400.2010.04.009

中图分类号：

学科分类号：

摘要：

The ASIP combines programmability of DSP and high speed of ASIC, and the parallel array processing system based on it plays an important role in the high-speed and real-time processing applications. An implementation of 1024 points FFT parallel processor based on the ASIP is presented in this paper. An ASIP with the reduced instruction set computer (RISC) architecture is designed as the processing element (PE), which constructs the kernel of the parallel processing system. In addition, the communication matrix is adopted to achieve the data exchange between PEs. Experimental results show that, compared with the typical DSP, the new proposed architecture improves the processing speed by 30%. Furthermore, this system has the advantages of larger parallel scale, greater function adaptability, relatively lower designing complexity and greater design reuse ability. So it can be achieved in a single FPGA in the form of SoC.

引用

页码：630 / 635

页数：5

共 9 条

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