Experimental and simulated results of room temperature single electron transistor formed by atomic force microscopy nano-oxidation process

被引：0

作者：

Gotoh, Yoshitaka ^{[1
]}

Matsumoto, Kazuhiko ^{[1
]}

Bubanja, Vladimir ^{[1
]}

Vazquez, Francisco ^{[1
]}

Maeda, Tatsuro ^{[1
]}

Harris, James S. ^{[2
]}

机构：

[1] Electrotechnical Laboratory MITI, 1-1-4 Umezono, Tsukuba, Ibaraki 305-8568, Japan

[2] Stanford University, Stanford, CA 94305, United States

来源：

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 2000年 / 39卷 / 5 B期

关键词：

Atomic force microscopy - Capacitance - Computer simulation - Mathematical models - Nanotechnology - Oxidation - Semiconductor device manufacture - Substrates - Temperature - Tunnel junctions;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A planar-type single electron transistor (SET) was fabricated by the atomic force microscopy (AFM) nano-oxidation process. The fabricated SET showed the Coulomb oscillation characteristic with the period of about 2 V at room temperature. From the three-dimensional simulation, it is found out that the smaller the SET island size, the smaller the tunnel junction capacitance, and the tunnel junction capacitance shows a weak dependence on the tunnel junction width. Using the analytical model, the reason for this weak dependence was clarified.

引用

页码：2334 / 2337

共 49 条

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