Research on variable rate modulator and its implementation on FPGA

被引：0

作者：

Zhai, Haitao ^{[1
]}

Xi, Zhipeng ^{[1
]}

Zhang, Eryang ^{[1
]}

机构：

[1] College of Electronic Science and Engineering, National University of Defense Technology

来源：

Guofang Keji Daxue Xuebao/Journal of National University of Defense Technology | 2014年 / 36卷 / 02期

关键词：

Bit rate; DAC; FPGA; Modulator; Parallel filtering; Variable rate;

D O I：

10.11887/j.cn.201402021

中图分类号：

学科分类号：

摘要：

A variable modulator scheme is presented. The hardware system adopting the proposed approach was accomplished based on field programmable gate array (FPGA). The proposed system can deal with signals with bit rate even varying from (13.5~300)Mbps continuously. By splitting the whole rate range into several small parts and filtering the input data with different interpolation times, the correctness of transferring all rates into the dealing range of digital analog convert (DAC) was ensured. The architecture of system was devised and the difficulties in hardware realization were analysed. The ways to solve the pivotal problem were particularly indicated. Realization on FPGA demonstrates the good performance of the proposed idea. The expansibility of system makes it easy to be applied in wider rate bound.

引用

页码：124 / 128

页数：4

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