A Low Power SAR ADC Design Based on Segmented Capacitor

被引：0

作者：

An S. ^{[1
,2
]}

Zhang L. ^{[2
]}

Wang B. ^{[2
]}

Wang S. ^{[2
]}

Yang R. ^{[1
]}

机构：

[1] School of Electronic and Information Engineering, Hebei University of Technology, Tianjin

[2] School of Information Science and Engineering, Hebei University of Science and Technology, Shijiazhuang

来源：

Yang, Ruixia (yangrx@hebut.edu.cn) | 2017年 / Tianjin University卷 / 50期

关键词：

Low power; Mismatch calibration; Offset calibration; Successive approximation register analog-to-digital converter;

D O I：

10.11784/tdxbz201604076

中图分类号：

学科分类号：

摘要：

According to the strict requirements of the current networking technology on power consumption, a low power successive approximation register analog-to-digital converter (SAR ADC) circuit based on segmented capacitor has been designed. The capacitor array is used to reduce the number of unit capacity and power consumption of the ADC needed by the whole CDAC. At the same time, the separation capacitor calibration technique is adopted to reduce the overall CDAC nonlinear correction and the disorder technology is adopted to reduce the imbalance of the comparator circuit. A 10-bit 10-Msample/s circuit prototype design and the corresponding layout design and verification work have been completed under the 0.18 μm CMOS process, with PAD chip for the whole area is 1 mm2. The simulation results show that when the chip converter is under the condition of correction with 4.89 MHz input signal frequency, the spurious free dynamic range (SFDR) is 61.43 dB, which is 54%, higher than without correction. The effective number of bits (ENOB) reached 9.9 bit, increased by 3.7 bit compared with that under the condition of non correction. The power consumption is only 255 μW at 1.8 V power supply. © 2017, Editorial Board of Journal of Tianjin University(Science and Technology). All right reserved.

引用

页码：850 / 855

页数：5

共 15 条

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