Simulation for strategic hardware Trojans testing

The increasing complexity of microcircuits, coupled with fabless manufacturing, have ushered in more possibilities for tiny hardware Trojans to be introduced during an IC's design or fabrication stages. Tools for generating test vectors assume a fault model. A model is presented where the inputs and outputs of an IC's gates are the fault sites. At these sites, stuck-at faults can occur such that an input or an output is either stuck-at-0 or stuck-at-1. For the three wires (A, B, and C) associated with this AND gate, five more stuck-at faults remain: C stuck-at-0, A stuck-at-0, A stuck-at-1, B stuck-at-0, and B stuck-at-1. In the presence of the hardware Trojan's two gates the circuit's functionality can change dramatically. The payload is triggered when the output of the NOR gate goes high. This causes the XOR gate to invert the AND gate's attempt to set BUS-SEL low. Instead of BUS-SEL being low, the resultant BUSSEL signal would go high-creating, as intended by the attacker, haphazard functionality for the circuit. Based on a game theory engine, the simulator considers the attacker’s and tester's strategies and utilities (cost and payoffs). It can display the ensuing game in matrix notation that allows tracking the attacker's possible actions and the accompanying utility of each action.