Design of the programmable neural network processor based on the transport triggered architecture

被引：0
作者：
Zhao B. [1 ]
Zhang L. [1 ]
Shi G. [1 ]
Huang R. [1 ]
Xu X. [1 ]
机构：
[1] School of Electronic Engineering, Xidian Univ., Xi'an
来源：
Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University | 2018年 / 45卷 / 04期
关键词：
Convolutional neural networks; Deep learning; Field programmable gate array; Parallel computing;
D O I：
10.3969/j.issn.1001-2400.2018.04.017
中图分类号：
学科分类号：
摘要：
The convolutional neural networks have the problems of structure diversity and large amounts of data exchange and computation. A transport triggered architecture based convolutional neural network processor is presented in this paper. The data transport network is constructed with multi-channel direct memory access channels, the multi-port memory and the specialized pooling data path, which solves the inefficient data exchange problem. Experimental results show that, although the proposed architecture is 11% slower than the streamline structure, it can adapt to a variety of convolutional neural networks and save 46.5% multipliers. Compared with the schemes presented in other papers except pipeline implementation, our design improves the data throughput rate by 40% at least. Besides, this system has advantages of parallel efficiency, programmable flexibility, online architecture reconfiguration, high processing speed, etc © 2018, The Editorial Board of Journal of Xidian University. All right reserved.
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页码：92 / 98
页数：6
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