Three-layer cooperative architecture for MPEG-2 video encoder LSI

被引：0

作者：

Ikeda, M. ^{[1
]}

Kondo, T. ^{[2
]}

Nitta, K. ^{[1
]}

Suguri, K. ^{[1
]}

Yoshitome, T. ^{[1
]}

Minami, T. ^{[1
]}

Naganuma, J. ^{[1
]}

Ogura, T. ^{[1
]}

机构：

[1] Ntt Cyber Space Lab., Yokosuka-shi, Japan

[2] Ntt Electronics Corp., Ebina-shi, Japan

来源：

IEICE Transactions on Electronics | 2000年 / E83-C卷 / 02期

关键词：

CMOS integrated circuits - Data transfer - Electric power supplies to apparatus - Embedded systems - Image coding - Image compression - Image quality - LSI circuits - Motion compensation - Video signal processing;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-μm four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.

引用

页码：170 / 178