共 26 条
- [21] Shi Y., Togawa N., Yanagisawa M., Ohtsuki T., Robust secure scan design against scan-based differential cryptanalysis, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, 20, 1, pp. 176-181, (2012)
- [22] Shiny M.I., Nirmala D.M., LFSR based secured scan design testability techniques, Journal of Procedia Computer Science, 115, 9, pp. 174-181, (2017)
- [23] Sudeendra K.K., Lodha K., Sahoo S.R., Mahapatra K.K., On-chip based secure output response compactor for scan-based attack resistance, International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), pp. 1-6, (2015)
- [24] Vithayathil M., Prabhu B., Ningthoujam R., Designing and modelling of a low-cost wireless telemetry system for deep brain stimulation studies, Indian Journal of Science and Technology, 12, 8, pp. 1-13, (2019)
- [25] Yang B., Wu K., Karri R., Scan based side channel attack on dedicated hardware implementations of data encryption standard, Proceedings of International Test Conference ITC, pp. 339-344, (2004)
- [26] Zhang J., A practical logic obfuscation technique for hardware security, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, 24, 3, pp. 1193-1197, (2016)