Direct measurement of capacitance parameters in nanometer-scale MOSFETs

被引：0

作者：

Inokawa, Hiroshi ^{[1
]}

Fujiwara, Akira ^{[2
]}

Nishiguchi, Katsuhiko ^{[2
]}

Ono, Yukinori ^{[2
]}

Satoh, Hiroaki ^{[1
]}

机构：

[1] Research Institute of Electronics, Shizuoka University, Naka-ku, Hamamatsu 432-8011

[2] NTT Basic Research Laboratories, NTT Corporation, Wakamiya, Atsugi-shi, Kanagawa Pref. 243-0198

来源：

IEEJ Transactions on Electronics, Information and Systems | 2008年 / 128卷 / 06期

关键词：

Capacitance parameter; Metal-oxide-semiconductor field-effect transistor (MOSFET); Single-electron charging effect;

D O I：

10.1541/ieejeiss.128.905

中图分类号：

学科分类号：

摘要：

A simple measurement method is proposed for extracting capacitances in nanometer-scale metal-oxide-semiconductor field-effect transistors (MOSFETs). The method utilizes two serially connected MOSFETs and an optional metal layer above the intermediate node between MOSFETs. Gate-drain overlap capacitance and capacitances around the intermediate node, including one related to the metal layer, can be obtained by measuring the transfer current when two MOSFETs are alternately turned on at high frequency. High sensitivity in the order of attofarad is demonstrated using silicon-on-insulator (SOI) MOSFETs with gate length of 140-300 nm and channel width of 320 nm. The proposed method is useful not only in optimizing the high-frequency performance of the scale-down devices, but also in estimating the instability (i.e. kTIC noise) and single-electron charging effect in nanometer-scale circuits. © 2008 The Institute of Electrical Engineers of Japan.

引用

页码：905 / 911+12

共 7 条

[1] Taur Y., Ning T.H., Fundamentals of Modern VLSI Devices, pp. 272-275, (1998)
[2] Natori K., Sano N., Scaling limit of digital circuits due to thermal noise, J. Appl. Phys., 83, 10, pp. 5019-5024, (1998)
[3] MOSIS Process Monitor
[4] Vitanov P., Schwabe U., Eisele I., Electrical characterization of feature sizes and parasitic capacitances using a single test structure, IEEE Trans. Electron Devices, ED-31, 1, pp. 96-100, (1984)
[5] Ichikawa F., Nagatomo Y., Katakura Y., Itoh M., Itoh S., Matsuhashi H., Ichimori T., Hirashita N., Baba S., Fully depleted SOI process and device technology for digital and RF applications, Solid-State Electron, 48, 6, pp. 999-1006, (2004)
[6] Fujiwara A., Zimmerman N.M., Ono Y., Takahashi Y., Current quantization due to single-electron transfer in Si-wire charge-coupled devices, Appl. Phys. Lett., 84, 8, pp. 1323-1325, (2004)
[7] Likharev K.K., Single-election devices and their applications, Proc. IEEE, 87, 4, pp. 606-632, (1999)

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