Adaptive interconnect models for transaction-level simulation

被引:0
作者
Salimi Khaligh, Rauf [1 ]
Radetzki, Martin [1 ]
机构
[1] Embedded Systems Engineering Group, Institute of Computer Architecture and Computer Engineering (ITI), Universitaet Stuttgart, Stuttgart 70569
来源
Lecture Notes in Electrical Engineering | 2009年 / 36 LNEE卷
关键词
Adaptive models; On-chip interconnect models; SystemC; Transaction level modeling;
D O I
10.1007/978-1-4020-9714-0_10
中图分类号
学科分类号
摘要
Transaction level models are constructed for efficient simulation of complex embedded systems and systems-on-chip. Traditionally, the use case of a transaction level model dictates its accuracy and abstraction level, which are fixed during simulation. Although the chosen level of accuracy may be required in some intervals, in some other intervals the model may simply be too accurate for the scenario being simulated. This makes the model a simulation bottleneck and unnecessarily impedes the simulation performance. In this contribution we present an adaptive approach for modeling interconnects. The abstraction level of an adaptive model dynamically adapts to the simulation scenario, increasing the simulation performance without sacrificing the accuracy. We have developed adaptive models for point-to-point, FIFO based communication channels widely used in modern GALS and multiprocessor systems as well as models for complex, pipelined buses. We have applied the proposed approach to two real-world communication protocols and developed adaptive models of the AMBA AHB bus and the Fast Simplex Link (FSL) in SystemC, based on the recent OSCI TLM 2 standard. Our experiments clearly show the increase in simulation performance compared to existing, non-adaptive models. © 2009 Springer Science+Business Media B.V.
引用
收藏
页码:149 / 165
页数:16
相关论文
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