共 50 条
[41]
Dynamic Electrothermal Macromodeling: an Application to Signal Integrity Analysis in Highly Integrated Electronic Systems
[J].
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY,
2013, 3 (07)
:1237-1243
[42]
The Influence of Pre-layer Processing on the Signal Integrity of 5G High Frequency Communication Multilayer LCP Lines
[J].
2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM),
2021,
[44]
Die-Package-PCB Signal Integrity Performance Debug of a High-Speed (25Gbps) Retimer: Simulation to Measurement Correlation
[J].
2020 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY AND SIGNAL & POWER INTEGRITY VIRTUAL SYMPOSIUM(IEEE EMC+SIPI),
2020,
:170-175
[45]
Signal-Power Integrity Co-Simulations of High Speed Systems via Chip-Package-PCB Co-Analysis Methodology
[J].
2013 14TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT),
2013,
:485-491
[46]
Impact of Worst-Case Excitation for DDR interface Signal and Power Integrity Co-Simulation
[J].
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS,
2020, 36 (03)
:365-374
[47]
Application of Machine Learning in De-embedding of Signal Integrity Parameters for High Speed Serial Link
[J].
2024 IEEE 8TH INTERNATIONAL TEST CONFERENCE INDIA, ITC INDIA 2024,
2024,
:90-94
[48]
Impact of Worst-Case Excitation for DDR interface Signal and Power Integrity Co-Simulation
[J].
Journal of Electronic Testing,
2020, 36
:365-374
[49]
Probe Card Design with Signal and Power Integrity for Wafer-level Application Processor Test in LPDDR Channel
[J].
2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC),
2016,
:2442-2448
[50]
Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net
[J].
2018 IEEE 22ND WORKSHOP ON SIGNAL AND POWER INTEGRITY (SPI),
2018,