Practical EBG application to multilayer PCB: Impact on signal integrity

被引:4
作者
Nisanci, M.H. [1 ]
De Paulis, F. [1 ]
Di Febo, Danilo [1 ]
Orlandi, A. [1 ]
机构
[1] UAq EMC Laboratory, Department of Industrial and Information Engineering, Economics, University of l'Aquila, L'Aquila
关键词
Electromagnetic band gap structures; Printed circuit boards; Signal integrity;
D O I
10.1109/MEMC.2013.6650084
中图分类号
学科分类号
摘要
In this paper, signal transmission performance of single ended and differential striplines between two parallel GND planes with embedded electromagnetic band gap (EBG) structure for noise isolation in high speed digital printed circuit boards (PCB) are studied. The performances in terms of |S11|, |S21|, |Sdd21| and |Scc21| are considered in function of the stack up cross section and position above the EBG. Practical considerations for the layout strategies are drawn. © 2013 IEEE Electromagnetic Compatibility Magazine.
引用
收藏
页码:82 / 87
页数:5
相关论文
共 50 条
[41]   Dynamic Electrothermal Macromodeling: an Application to Signal Integrity Analysis in Highly Integrated Electronic Systems [J].
d'Alessandro, Vincenzo ;
de Magistris, Massimiliano ;
Magnani, Alessandro ;
Rinaldi, Niccolo ;
Russo, Salvatore .
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2013, 3 (07) :1237-1243
[42]   The Influence of Pre-layer Processing on the Signal Integrity of 5G High Frequency Communication Multilayer LCP Lines [J].
Lai, Haiqi ;
Chen, Tao ;
Yang, Guannan ;
Zhang, Yu ;
Cui, Chengqiang .
2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM), 2021,
[43]   Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity [J].
Tsuchiya, Akira ;
Hiratsuka, Akitaka ;
Inoue, Toshiyuki ;
Kishine, Keiji ;
Onodera, Hidetoshi .
IEICE TRANSACTIONS ON ELECTRONICS, 2019, E102C (07) :573-579
[44]   Die-Package-PCB Signal Integrity Performance Debug of a High-Speed (25Gbps) Retimer: Simulation to Measurement Correlation [J].
Tang, Tony ;
Wray, Bridger ;
Murugan, Rajen .
2020 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY AND SIGNAL & POWER INTEGRITY VIRTUAL SYMPOSIUM(IEEE EMC+SIPI), 2020, :170-175
[45]   Signal-Power Integrity Co-Simulations of High Speed Systems via Chip-Package-PCB Co-Analysis Methodology [J].
Wen Jiwei ;
Jing Weiping .
2013 14TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2013, :485-491
[46]   Impact of Worst-Case Excitation for DDR interface Signal and Power Integrity Co-Simulation [J].
Yu, Dongzhe ;
Wang, Han ;
Xu, Jiangtao .
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2020, 36 (03) :365-374
[47]   Application of Machine Learning in De-embedding of Signal Integrity Parameters for High Speed Serial Link [J].
Pandey, Maneesh ;
Goyal, Mohit ;
Dash, Ajay .
2024 IEEE 8TH INTERNATIONAL TEST CONFERENCE INDIA, ITC INDIA 2024, 2024, :90-94
[48]   Impact of Worst-Case Excitation for DDR interface Signal and Power Integrity Co-Simulation [J].
Dongzhe Yu ;
Han Wang ;
Jiangtao Xu .
Journal of Electronic Testing, 2020, 36 :365-374
[49]   Probe Card Design with Signal and Power Integrity for Wafer-level Application Processor Test in LPDDR Channel [J].
Song, Jinwook ;
Lee, Eunjung ;
Kim, Jonghoon ;
Park, Shinyoung ;
Kim, Joungho ;
Park, Jung Keun ;
Park, Jong Hyun ;
Bang, Yoon Hee ;
Kim, Hyun Mm ;
Kim, Young Bu ;
Nam, Seungki .
2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2016, :2442-2448
[50]   Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net [J].
Tsuchiya, Akira ;
Hiratsuka, Akitaka ;
Inoue, Toshiyuki ;
Kishine, Keiji ;
Onodera, Hidetoshi .
2018 IEEE 22ND WORKSHOP ON SIGNAL AND POWER INTEGRITY (SPI), 2018,