Hybrid reduction technique for efficient simulation of linear/nonlinear mixed circuits

被引：0

作者：

Mine, Takashi ^{[1
]}

Kubota, Hidemasa ^{[1
]}

Kamo, Atsushi ^{[2
]}

Watanabe, Takayuki ^{[3
]}

Asai, Hideki ^{[1
]}

机构：

[1] Department of Systems Engineering, Faculty O F Engineering, Shizuoka University, 3-5-1, Johoku, Hamamatsu-shi, 432-8561, Japan

[2] Sony LSI Design Inc. Gohdo-cho134, Hodogaya-ku, Yokohama, Kanagawa 240-0005, Japan

[3] School of Administration and Informatics, University of Shizuoka, 52-1, Yada, Shizuoka-shi, 422-8526, Japan

来源：

Proc. Des. Autom. Test Eur. DATE | / 1327-1332期

关键词：

Compendex;

D O I：

1269079

中图分类号：

学科分类号：

摘要：

Timing circuits - Circuit simulation - Iterative methods - Linear transformations

引用