Performance analysis of novel domino XNOR gate in sub 45nm CMOS technology

被引:0
|
作者
机构
[1] Pandey, Amit Kumar
[2] Mishra, Ram Awadh
[3] Nagaria, Rajendra Kumar
来源
| 1600年 / World Scientific and Engineering Academy and Society, Ag. Ioannou Theologou 17-23, Zographou, Athens, 15773, Greece卷 / 12期
关键词
Threshold voltage;
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
相关论文
共 50 条
  • [1] A novel current reference in 45nm cmos technology
    Nagulapalli, R.
    Hayatleh, K.
    Barker, S.
    Zourob, S.
    Venkatareddy, A.
    PROCEEDINGS OF THE 2017 IEEE SECOND INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND COMMUNICATION TECHNOLOGIES (ICECCT), 2017,
  • [2] Double-Gate CMOS evaluation for 45nm technology node
    Chiang, MH
    An, JX
    Krivokapic, Z
    Yu, B
    NANOTECH 2003, VOL 2, 2003, : 326 - 329
  • [3] Design and Analysis of Leakage Current and Delay for Double Gate MOSFET at 45nm in CMOS Technology
    Manorama
    Shrivastava, Pavan
    Akashe, Shyam
    7TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND CONTROL (ISCO 2013), 2013, : 301 - 306
  • [4] Metal gate technology for 45nm and beyond
    Shibahara, Kentaro
    2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2006, : 105 - 106
  • [5] Design and Analysis of Tunable Analog Circuit Using Double Gate MOSFET at 45nm CMOS Technology
    Kushwah, Ravindra Singh
    Akashe, Shyam
    PROCEEDINGS OF THE 2013 3RD IEEE INTERNATIONAL ADVANCE COMPUTING CONFERENCE (IACC), 2013, : 1589 - 1594
  • [6] Leakage Power Reduction for Domino Circuits in 45nm CMOS Technologies
    Pandey, A. K.
    Kaur, S.
    Mishra, R. A.
    Nagaria, R. K.
    2012 2ND INTERNATIONAL CONFERENCE ON POWER, CONTROL AND EMBEDDED SYSTEMS (ICPCES 2012), 2012,
  • [7] Advanced CMOS technology beyond 45nm node
    Kawanaka, Shigeru
    Hokazono, Akira
    Yasutake, Nobuaki
    Tatsumura, Kosuke
    Koyama, Masato
    Toyoshima, Yoshiaki
    2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 164 - +
  • [8] FOREMOST project will integrate 45nm CMOS technology
    不详
    ELECTRONICS WORLD, 2007, 113 (1852): : 6 - 6
  • [9] High Performance Digital to Analog Converter Using CMOS 45nm Technology
    Raju, David Solomon Y.
    Shyamala, K.
    Sumalatha, Ch
    Sunilkumar, J.
    PROCEEDINGS OF THE 6TH INTERNATIONAL CONFERENCE ON INVENTIVE COMPUTATION TECHNOLOGIES (ICICT 2021), 2021, : 357 - 361
  • [10] Design of pn mixed pull-down network domino XOR gate in 45nm technology
    VLSI and System Laboratory, Beijing University of Technology, Beijing 100022, China
    不详
    Pan Tao Ti Hsueh Pao, 2008, 12 (2443-2447): : 2443 - 2447