A novel FPN reduction technology of logarithmic APS based on wide dynamic range CMOS image sensor

被引：0

作者：

机构：

[1] Liu, Ji-Yang

[2] Yao, Su-Ying

[3] Zhao, Yi-Qiang

[4] Zhang, Wei

[5] Zhang, Sheng-Cai

[6] Li, Shu-Rong

[7] Xu, Jiang-Tao

来源：

Liu, J.-Y. (com35@vip.sina.com) | 2005年 / Guojia Jiaowei Quanguo Gaoxiao Chuangan Jishu Yanjiuhui卷 / 18期

关键词：

CMOS integrated circuits - Sampling - Transistors;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

The logarithmic response CMOS image sensor provides a wide dynamic range (around 120dB), but its drawback in logarithmic image sensor design is the lack of simple fixed pattern noise (FPN) cancellation scheme. A Log-APS is employed for CMOS image sensor to achieve wider dynamic range than linear-APS. A novel FPN reduction technology is introduced to enable pixel FPN reduction in a logarithmic mode image sensor by additional transistor with double sampling circuit. This is a significantly high reduction in the FPN levels and it suggests that the double sampling technique with additional switch transistor is an efficient method for FPN reduction in the logarithmic mode of pixel output.

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