Low Power and Least Significant Bit-First Successive-Approximation Analog-to-Digital Converter for Implantable Medical Devices

Aiming at the ultra-low power consumption design of the indispensable analog-to-digital converter (ADC) in implantable medical devices, based on the low-power-consumption successive-approximation SAR ADC, a least significant bit (LSB)-first SAR ADC is presented. The LSB-first quantitative logic is mainly used for biological signals of low mobility, such as electrocardiosignal. Under the condition of fixed resolution and sampling rate, the number of quantization is adjusted according to the amplitude of the varying signal, so as to achieve the purpose of reducing power consumption and compressing data amount. Only a minimum number of three quantizations is required to obtain a quantitative result when the signal in on the baseline or varies slowly. Global Foundry 0.18-μm standard CMOS process is used to design the circuit and layout of the ADC. The post-simulation results show that at the power supply voltage of 1.8 V and the sampling rate of 1 kHz, the effective bits are 9.6 bits, and the average current power consumption of the core circuit is 64-131 nA. The proposed LSB-first ADC can achieve high quantization accuracy while significantly reducing power consumption, and it is especially suitable for application in analog-to-digital conversion of low-mobility biological signals for implantable or wearable medical devices. © 2020, Editorial Office of Journal of Xi'an Jiaotong University. All right reserved.