High performance device design through parasitic junction capacitance reduction and junction leakage current suppression beyond 0.1 μm technology

被引：0

作者：

Dept. of Technology Development, Chartered Semiconductor Mfg. Ltd., 60 Woodlands Indust. Park D. St. 2, Singapore 738406, Singapore ^{[1
]}

机构：

来源：

| 1600年 / 2144-2148卷 / April 2003期

关键词：

Compendex;

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摘要：

Capacitance - Integrated circuit layout - Leakage currents - MOSFET devices - Optimization - Oscillators (electronic) - Semiconductor device manufacture - Transistors

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