Design of on-line clock jitter fault detection circuit for time-error-tolerant system

One of the major obstacles encountered in design of a system on chip (SoC) arises from the highfault rate of clock distribution network in embedded intellectual property (IP) cores. With technology scaling, the geometries of devices approach its physical limits of operation, clock signals in SoCs will be susceptible to various noise sources such as coupling noise, crosstalk, process variations, etc. Designing such a system under uncertainty becomes a challenge, as it is difficult to predict the time behavior of the system. In this paper we present an aggressive method to on-line detect jitter faults of clock signal that are due to defects caused by noise in high speed SoCs. Only fourteen MOS transistors and two minor capacitors are used for whole circuit. The technique of time-to-voltage conversion is employed for transforming the time jitter error to deviation of voltage, which is more convenient in contrast with the conservative clock fault detection structure methodology. The proposed circuit can detect jitter error of the digital clock signal for different applications. Simulation-based results show that the proposed circuit can be integrated into the nano-electronic SoC applications to achieve the online clock jitter fault detection, and its maximal frequency can reach 800MHz.