Data Memory Structure and Management Strategy of Reconfigurable System for Radar

被引：0
作者：
Liu B. [1 ]
Wang X. [1 ]
Zhang D. [1 ]
Ge W. [1 ]
机构：
[1] National ASIC System Engineering Research Center, Southeast University, Nanjing
来源：
| 1600年 / Shanghai Jiaotong University卷 / 51期
关键词：
Data management strategy; Data memory structure; Reconfigurable system;
D O I：
10.16183/j.cnki.jsjtu.2017.05.017
中图分类号：
学科分类号：
摘要：
Aiming at the serious problems of access conflicts and low access efficiency, this paper proposes a hierarchical memory structure and data management strategy based on linear varying step-size for radar sub-algorithms. By establishing the logical mapping strategy between the reconfigurable arrays and the multi-bank memory, our design successfully reduces the access conflicts when the tasks assigned on different arrays fetch the required data in parallel and achieves a higher throughput. Consequently, the data access performance of the reconfigurable system is improved. Based on the TSMC 45 nm complementary metal oxide semiconductor (CMOS) technology, the memory access performance can be increased highly for radar sub-algorithms. An example of the 256-point to 64×210-point fast Fourier transform (FFT) shows that the performance of the reconfigurable system compared to the representative parallel memory architecture (PMA) approach can be improved by 26.09% to 54.60%. © 2017, Shanghai Jiao Tong University Press. All right reserved.
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页码：628 / 635
页数：7
相关论文
共 14 条
  • [11] Duan R., Research on embedded reconfigurable DSP architecture, (2005)
  • [12] Liu D.J., Yin S.Y., Liu L.B., Et al., Polyhedral model based mapping optimization of loop nests for CGRAs, 50th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1-8, (2013)
  • [13] Yin S.Y., Liu D.J., Peng Y., Et al., Improving nested loop pipelining on coarse-grained reconfigurable architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24, 2, pp. 1-14, (2015)
  • [14] Zhang B.T., On-chip high performance embedded computing-soft baseband application parallel processing model & architecture, (2011)
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