SpMT WaveCache: Exploiting speculative multithreading for dataflow computer

被引:0
作者
Pei, Song-Wen [1 ]
Wu, Bai-Feng [1 ]
机构
[1] School of Computer Science, Fudan University
来源
Jisuanji Xuebao/Chinese Journal of Computers | 2009年 / 32卷 / 07期
关键词
Dynamic dataflow computer; Speculative multithreading (SpMT); Transactional memory; WaveScalar;
D O I
10.3724/SP.J.1016.2009.01382
中图分类号
学科分类号
摘要
Speculative Multithreading (SpMT) increases the performance by means of executing multithreads speculatively to exploit thread-level parallelism. The authors expanded the transactional memory system of WaveCache by adding extra hardware components, such as Thread Synchronization Unit (TSU), Thread Context Table (TCT) and Thread Memory History (TMH), to improve the performance of SpMT WaveCache which is built on WaveScalar instruction set architecture (ISA). Furthermore, a novel two-levels commit method is proposed to support submitting thread-level transactions. Finally, the SpMT WaveCache is evaluated with 6 real benchmarks selected from SPEC, Mediabench and Mibench benchmarks. According to the experimental results, the SpMT WaveCache outperforms superscalar architecture ranging from 2X to 3X, and it also performs greater gain over original WaveCache and Transactional WaveCache. Therefore, the SpMT WaveCache is a good way to exploit thread-level parallelism of dynamic dataflow computer.
引用
收藏
页码:1382 / 1392
页数:10
相关论文
共 25 条
  • [1] Swanson S., Schwerin A., Mercaldi M., Et al., The WaveScalar architecture, ACM Transactions on Computer Systems (TOCS), 25, 2, pp. 1-54, (2007)
  • [2] Swanson S., The WaveScalar architecture, (2006)
  • [3] Buck I., Foley T., Horn D., Et al., Brook for GPUs: Stream computing on graphics hardware, ACM Transactions on Graphics (TOG), 23, 3, pp. 777-786, (2004)
  • [4] Pellerin D., Thibault S., Practical FPGA Programming in C, (2005)
  • [5] Mercaldi M., Swanson S., Petersen A., Et al., Instruction scheduling for a tiled dataflow architecture, Proceedings of the 12th International Conference on Architecture Support for Programming Languages and Operating Systems (ASPLOS), pp. 141-150, (2006)
  • [6] Marzulo L., Franca F., Costa V.S., Transactional WaveCache: Towards, speculative and out-of-order dataflow execution of memory operations, Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, pp. 183-190, (2008)
  • [7] Wu B.F., Pei S.W., Zhu K., Yu Q., Data-driven multithreading programming model based on DDF, Proceedings of the 2nd International Conference on Pervasive Computing and Applications (ICPCA), pp. 577-581, (2007)
  • [8] Tullsen D., Eggers S., Levy H., Simultaneous multithreading maximizing on-chip parallelism, Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA), pp. 392-403, (1995)
  • [9] Franklin M., Sohi G., The expandable split window paradigm for exploiting fine grain parallelism, Proceedings of the 19th Annual International Symposium on Computer Architecture (ISCA), pp. 58-67, (1992)
  • [10] Sohi G., Breach S., Vijaykumar T.N., Multiscalar processors, Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA), pp. 414-425, (1995)