Performance degradation mechanism of p-GaN HEMT under dynamic gate stress

被引：0

作者：

Huang J. ^{[1
]}

Li S. ^{[1
]}

Zhang C. ^{[1
]}

Liu S. ^{[1
]}

Sun W. ^{[1
]}

机构：

[1] National ASIC System Engineering Research Center, Southeast University, Nanjing

来源：

Dongnan Daxue Xuebao (Ziran Kexue Ban)/Journal of Southeast University (Natural Science Edition) | 2022年 / 52卷 / 06期

关键词：

degradation of on-state resistance; dynamic gate stress; gallium nitride based p-type gate high electron mobility transistor (p-GaN HEMT); test circuit;

D O I：

10.3969/j.issn.1001-0505.2022.06.013

中图分类号：

学科分类号：

摘要：

To study the electrical performance degradation mechanism of gallium nitride based p-type gate high electron mobility transistor (p-GaN HEMT) under dynamic gate stress, a fast switching test circuit controlled by two switching devices is designed, and the dynamic on-state resistance (Ron) of the device under test (DUT) is rapidly measured within 300 ns after the dynamic gate stress is applied. Furthermore, comparative experiments combined with simulation analysis are conducted. The results show that when the effective dynamic gate stress is applied for 300 s, the threshold voltage of DUT remains basically unchanged, while the Ron increases significantly with the increase of the time and the frequency of the stress, and the highest degradation rate reaches up to 10.82%. Hole hot carriers are injected into the channel layer of DUT during turn-on and turn-off stages, eventually leading to the degradation of Ron. However, due to the absence of hot carriers during the on-state and off-state procedures, the electrical parameters of the device remain stable. In conclusion, the Ron degradation under dynamic gate stress is mainly induced by the hole hot carrier injection during turn-on and turn-off stages. © 2022 Southeast University. All rights reserved.

引用

页码：1130 / 1136

页数：6

共 17 条

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