Multiple frequency digital phase-locked loop based on multi-phase clock divider with constant pulse interval

被引：0
作者：
Yahara M. [1 ]
Fujimoto K. [2 ]
Kiyota H. [2 ]
机构：
[1] Tokai University Fukuoka Junior College, 1-9-1, Taku, Munakata, Fukuoka
[2] School of Industrial and Welfare Engineering, Tokai University, 9-1-1, Toroku, Higashi-ku, Kumamoto-shi, Kumamoto
来源：
IEEJ Transactions on Electronics, Information and Systems | 2018年 / 138卷 / 04期
基金：
日本学术振兴会;
关键词：
Constant pulse interval; Multi-phase clock; Multiple frequency; PLL;
D O I：
10.1541/ieejeiss.138.387
中图分类号：
学科分类号：
摘要：
In the mobile communication equipment, the clock generator for driving each system is required to have a fast pull-in time, multiple signal of constant pulse interval, synchronization range, low output jitter, and wide lock-in range characteristics. In this paper, multiple frequency MC-DCPLL is proposed. In this loop, the pulse width error of the multiplied output signal is a time within one phase difference of the multi-phase clock regardless of the multiplication ratio. The output jitter in the steady state is always within one phase difference of the multi-phase clock. Since it is a control method by dividing ratio changeable type, the lock-in range is extremely wide. Also, the initial pull-in time is always completed in one cycle of the input signal without being influenced by the multiplication ratio. It is clarified by theory and simulation that these characteristics can be obtained. From the above, the versatility of the proposed multiple frequency MC-DCPLL is extremely high, and it can be expected to be used for clock sources etc. in various mobile communication equipment systems. © 2018 The Institute of Electrical Engineers of Japan.
引用
收藏
页码：387 / 394
页数：7
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