共 50 条
- [1] Delay and energy efficient design of an on-chip bus with repeaters using a new spatial and temporal encoding technique Pan Tao Ti Hsueh Pao, 2008, 4 (724-732):
- [3] Delay and energy efficient data transmission for on-chip buses IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006, : 355 - +
- [4] On-chip bus encoding for power minimization under delay constraint 2007 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 57 - +
- [5] RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 4134 - 4137
- [6] Low power encoding for coupled on-chip buses Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3, 2003, : 552 - 555
- [7] Delay and energy efficient design of on-chip encoded bus with repeaters 21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, : 377 - 382
- [9] Partitioned hybrid encoding to minimize on-chip energy dissipation of wide microprocessor buses 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, 2007, : 127 - +
- [10] Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 592 - 595