Design and Implementation of Memory Access Fast Switching Structure in Cluster-Based Reconfigurable Array Processor

被引：0

作者：

Shan R. ^{[1
]}

Jiang L. ^{[2
]}

Deng J. ^{[2
]}

Li X. ^{[3
]}

Shen X. ^{[1
]}

机构：

[1] School of Micro-electronics, Xidian University, Xi'an

[2] School of Electronic Engineering, Xi'an University of Posts and Telecommunication, Xi'an

[3] School of Computer Science & Technology, Xi'an University of Posts and Telecommunication, Xi'an

来源：

Journal of Beijing Institute of Technology (English Edition) | 2017年 / 26卷 / 04期

基金：

中国国家自然科学基金;

关键词：

Array processor; Distributed memory; Memory access; Switching structure;

D O I：

10.15918/j.jbit1004-0579.201726.0409

中图分类号：

学科分类号：

摘要：

Memory access fast switching structures in cluster are studied, and three kinds of fast switching structures (FS, LR2SS, and LAPS) are proposed. A mixed simulation test bench is constructed and used for statistic of data access delay among these three structures in various cases. Finally these structures are realized on Xilinx FPGA development board and DCT, FFT, SAD, IME, FME, and de-blocking filtering algorithms are mapped onto the structures. Compared with available architectures, our proposed structures have lower data access delay and lower area. © 2017 Editorial Department of Journal of Beijing Institute of Technology.

引用

页码：494 / 504

页数：10

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