Assessing thermal resistance in fusion bond layers of 3D heterogeneous electronics packaging
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作者:
Zandavi, S. Hadi
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Intel Corp, Technol Dev Assembly Pathfinding & Prototyping Lin, 5000 W Chandler Blvd, Chandler, AZ 85226 USAIntel Corp, Technol Dev Assembly Pathfinding & Prototyping Lin, 5000 W Chandler Blvd, Chandler, AZ 85226 USA
Zandavi, S. Hadi
[1
]
Schmidt, Aaron
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Fourier Sci LLC, 128 Magazine St, 12A, Cambridge, MA 02139 USAIntel Corp, Technol Dev Assembly Pathfinding & Prototyping Lin, 5000 W Chandler Blvd, Chandler, AZ 85226 USA
Schmidt, Aaron
[2
]
Brun, Xavier
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Intel Corp, Technol Dev Assembly Pathfinding & Prototyping Lin, 5000 W Chandler Blvd, Chandler, AZ 85226 USAIntel Corp, Technol Dev Assembly Pathfinding & Prototyping Lin, 5000 W Chandler Blvd, Chandler, AZ 85226 USA
Brun, Xavier
[1
]
机构:
[1] Intel Corp, Technol Dev Assembly Pathfinding & Prototyping Lin, 5000 W Chandler Blvd, Chandler, AZ 85226 USA
[2] Fourier Sci LLC, 128 Magazine St, 12A, Cambridge, MA 02139 USA
We investigated thermal management challenges in semiconductor devices that use fusion bonding, with a focus on measuring the thermal resistance of the bonded interface. Starting with two fusion-bonded silicon wafers, we thinned the top wafer to below 100 mu m and used frequency domain thermoreflectance to measure the effective thermal boundary resistance of the fusion bond. We established the measurement uncertainty with a multilayer thermal diffusion model, considering the effects of the top Si layer thickness and laser spot size. The thermal boundary resistance was measured to be 0.2 and 0.5 m(2)K/MW for two types of bonded wafers, with total SiO2 film thicknesses of 200 and 470 nm at the fusion bond layer, respectively. We also created defects at the interface and imaged these defects with the thermal phase response at specific frequencies chosen according to a thermal model. The method described can be applied to other types of wafer-to-wafer or die-to-die bonding including direct, polymeric, and metallic bonds.