A high speed, optimized multiplier architecture for a DF-ECC processor

被引:0
作者
机构
[1] RNSIT, Dept.of ECE, VTU, PESCE, Mandya, Karnataka
[2] Department of E and C Engineering. VTU, PESCE, Mandya, Karnataka
来源
| 1600年 / UK Simulation Society, Clifton Lane, Nottingham, NG11 8NS, United Kingdom卷 / 14期
关键词
AES; DF; DF-; ECC; FA; FPGA; GF; LFSR; M1; M2;
D O I
10.5013/IJSSST.a.14.02.06
中图分类号
学科分类号
摘要
This paper presents a High speed, optimized multiplier architecture for a dual-field (DF) processor for elliptic curve cryptography (ECC). This processor can support the required operations in both galois prime field GF(p) and binary field GF(2m). The performance of the processor is enhanced by the judicious selection of proper type of coordinates in the arithmetic unit. The arithmetic unit is designed to provide dual-field multiplication and addition. The FPGA synthesis results show that the proposed dual-field ECC processor with Karatsuba method can reach a speed up to 124 MHz, consumes a power of 1091mW and occupies 3066 slices. © 2013, UK Simulation Society. All rights reserved.
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页码:35 / 41
页数:6
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