A 0.18μm CMOS based programmable integer-fractional combined frequency divider for frequency synthesizer of multi-standard wireless systems

被引：0

作者：

Xiangning, Fan ^{[1
]}

Bin, Li ^{[1
]}

Zhigong, Wang ^{[1
]}

机构：

[1] Institute of RF- and OE-ICs, School of Information Science and Engineering, Southeast University, Nanjing

来源：

Advances in Information Sciences and Service Sciences | 2012年 / 4卷 / 23期

关键词：

Frequency divider; MASH; 1-1-1; Multi-standard frequency synthesizer; Pulse-swallow counter;

D O I：

10.4156/AISS.vol4.issue23.13

中图分类号：

学科分类号：

摘要：

This paper first presents the architecture of a frequency synthesizer which can support multistandard wireless systems of GPS, Galileo, and WCDMA standards. Then, a programmable integer/fractional combined frequency divider (CFD), which is the key building block of the proposed frequency synthesizer, is designed and implemented by using 0.18μm RF CMOS process. The CFD mainly consists of an integer-N frequency divider and a 3rd Δ-Σ modulator for fractional frequency division. The integer-N frequency divider is based on pulse-swallow counter-type architecture to allow division ratio range from 512 to 767. For 3rd Δ-Σ modulator, the state of art Multi-Stage-Noise- Shaping (MASH) 1-1-1 structure is used for good shaping of quantization noise. With a 1.8V voltage supply, the CFD exhibits an operating frequency range from 0.5 to 6GHz and draws a current of 2.2mA at the input frequency of 4.5GHz. The measurement results indicate that the programmable integer/fractional combined frequency divider works well and can be used for the proposed multistandard frequency synthesizer.

引用

页码：104 / 111

页数：7

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