Towards Open-HW: A platform to design, share and deploy FPGA accelerators in low cost

被引：0
作者：
Zhao Q. [1 ]
Amagasaki M. [1 ]
Iida M. [1 ]
Kuga M. [1 ]
Sueyoshi T. [1 ]
机构：
[1] Kumamoto University, Kumamoto
来源：
IPSJ Transactions on System LSI Design Methodology | 2017年 / 10卷
关键词：
FPGA; Hardware acceleration; Open-source hardware;
D O I：
10.2197/ipsjtsldm.10.63
中图分类号：
学科分类号：
摘要：
Field-programmable gate array (FPGA) is a promising technology for the implementing of high-performance and power-efficient cloud computing by serving dedicated hardware as co-processor to accelerate loads on CPUs. However, developing an FPGA-based system is challenging because the complexity of the hardware and software co-design. In this paper, we propose a platform named hCODE to simplify the design, share, and deployment of FPGA accelerators. First, we adopt a shell-and-IP design pattern to improve the reusability and the portability of accelerator designs. Second, we implement an open accelerator repository to bridge hardware development and software development on one platform. On the hCODE platform, hardware developers can provide designs that follow hCODE specifications, which allowing software engineers to easily search, download, and integrate accelerators in their applications without caring about the hardware details. © 2017 Information Processing Society of Japan
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页码：63 / 70
页数：7
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