Design and implementation of efficient FIR filter based on FPGA

被引：0

作者：

Jiang, Li-Ping ^{[1
]}

Tan, Xue-Qin ^{[1
]}

Wang, Jian-Xin ^{[1
]}

机构：

[1] School of Electronic Engineering and Optoelectronic Technology, NUST, Nanjing 210094, China

来源：

Nanjing Li Gong Daxue Xuebao/Journal of Nanjing University of Science and Technology | 2007年 / 31卷 / 01期

关键词：

Field programmable gate arrays (FPGA) - FIR filters - Impulse response - MATLAB - Speed;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

This paper introduces the theories and common implementation methods of FIR (Finite impulse response) digital filter. An efficient implementation design based on FPGA is presented. Symmetrical structure, special multiplication operation, canonic signed digit encoding, cascade technology and pipelining technology are used to improve the conventional design methods. The design is simulated with the FPGA chip, Quartus II and Matlab software. The simulation result shows that this technique has such advantages as fast operation speed and economizing of devices. Its performance is much better than the conventional methods'.

引用

页码：125 / 128

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