Double-Sided Integrated GaN Power Module with Double Pulse Test (DPT) Verification

被引：0
作者：
Sinha S.S. [1 ]
Cheng T.-H. [1 ]
Hopkins D.C. [1 ]
机构：
[1] Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC
来源：
Journal of Microelectronics and Electronic Packaging | 2023年 / 20卷 / 02期
关键词：
coupling capacitance; Double Pulse Test; GaN power module; substrate current; thin substrate;
D O I：
10.4071/001c.81980
中图分类号：
学科分类号：
摘要：
Wide Bandgap devices (WBG) have led to an era of high-speed and high-voltage operations that were not previously achievable with silicon devices. However, packaging these devices in the power module has been a challenge due to higher switching rates, which can cause several amperes of displacement current to flow through the parasitic capacitance of the package, thus impacting the gate driver operation and the switching ability of the device. The severity of this current increases in thin packaging substrates, unlike the traditional inorganic substrates, e.g., Direct Bond Copper (DBC) and thus, a thorough investigation is needed before it can be used with WBG semiconductors. The objective of this article is to discuss ways to reduce as well as manipulate the parasitic capacitance at different locations in the power modules to reduce the magnitude of the peak and Root Mean Square (RMS ) value of the displacement current and have a better gate drive signal and power waveform. To study this, a Double Pulse Test (DPT) simulation study has been conducted to show how an intelligent distribution of parasitic capacitance benefits the device functioning. This has been validated through experimental fabrication and DPT of dense power module following proposed guidelines. A detailed description of the design of a high-speed capable DPT circuit and measurement setup has been specified to show the steps needed for reliable testing and measurement. © 2023 International Microelectronics Assembly and Packaging Society.
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页码：71 / 81
页数：10
相关论文
共 23 条
  • [1] Yoder M.N., Wide bandgap semiconductor materials and devices, IEEE Transactions on Electron Devices, 43, 10, pp. 1633-1636, (1996)
  • [2] Tiwari S., Midtgard O.-M., Undeland T.M., Comparative evaluation of a commercially available 1.2 kV SiC MOSFET module and a 1.2 kV Si IGBT module, IECON 2016-42nd Annual Conference of the IEEE Industrial Electronics Society, pp. 1093-1098, (2016)
  • [3] Rothmund D., Ortiz G., Kolar J.W., SiC-based unidirectional solid-state transformer concepts for directly interfacing 400V DC to Medium-Voltage AC distribution systems, 2014 IEEE 36th International Telecommunications Energy Conference (INTELEC), pp. 1-9, (2014)
  • [4] Chowdhury S., Gurpinar E., Ozpineci B., Characterization and Analysis of Insulated Metal Substrate-Based SiC Power Module for Traction Application, 2020 IEEE Energy Conversion Congress and Exposition (ECCE), pp. 195-202, (2020)
  • [5] Chasserio N., Guillemet-Fritsch Sophie, Lebey Thierry, Dagdag S., Ceramic Substrates for Hightemperature Electronic Integration, Journal of Electronic Materials, 38, pp. 164-174, (2009)
  • [6] Zhao X., Et al., Flexible epoxy-resin substrate based 1.2 kV SiC half bridge module with ultra-low parasitics and high functionality, 2017 IEEE Energy Conversion Congress and Exposition (ECCE), pp. 4011-4018, (2017)
  • [7] Lee H., Design and demonstration of SiC 3D stacked power module with superior electrical parasitics and thermal performances, (2020)
  • [8] Meisser M., Schmenger M., Blank T., Parasitics in power electronic modules: how parasitic inductance influences switching and how it can be minimized, Proceedings of the PCIM Europe 2015
  • [9] International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, pp. 1-8, (2015)
  • [10] Mouawad B., Li J., Castellazzi A., Friedrichs P., Johnson C.M., Low parasitic inductance multi-chip SiC devices packaging technology, 2016 18th European Conference on Power Electronics and Applications (EPE'16 ECCE Europe), pp. 1-7, (2016)
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