Two-level scratchpad memory architectures to achieve time predictability and high performance

被引：2
作者：
Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond [1 ]
VA, United States
机构：
[1] Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA
来源：
Zhang, Wei | 1600年 / Korean Institute of Information Scientists and Engineers卷 / 08期
关键词：
Hard real-time systems; Scratch-pad memory; Time predictability;
D O I：
10.5626/JCSE.2014.8.4.215
中图分类号：
学科分类号：
摘要：
In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable twolevel scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratchpad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied. © 2014. The Korean Institute of Information Scientists and Engineers.
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页码：215 / 227
页数：12
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