共 37 条
[1]
Zhang W., Li T., Managing multi-core soft-error reliability through utility-driven cross domain optimization, Proceedings of ASAP, pp. 132-137, (2008)
[2]
Mukherjee S.S., Weaver C., Emer J., Reinhardt S.K., Austin T., A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, Proceedings of MICRO, (2003)
[3]
Rivers J.A., Bose P., Kudva P., Wellman J.D., Sanda P.N., Et al., Phaser: Phased methodology for modeling the system-level effects of soft errors, IBM J. Res. Dev., 52, 3, pp. 293-306, (2008)
[4]
Yoon D.H., Erez M., Memory mapped ECC: Low-cost error protection for last level caches, Proceedings of ISCA, pp. 116-127, (2009)
[5]
Kim S., Reducing area overhead for error-protecting large L2/L3 caches, IEEE Trans. Comput., 58, 3, pp. 300-310, (2009)
[6]
Zhou P., Zhao B., Yang J., Zhang Y., A durable and energy efficient main memory using phase change memory technology, Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 14-23, (2009)
[7]
Lee B.C., Ipek E., Mutlu O., Burger D., Architecting phase change memory as a scalable dram alternative, Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 2-13, (2009)
[8]
Qureshi M.K., Srinivasan V., Rivers J.A., Scalable high performance main memory system using phase-change memory technology, Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 24-33, (2009)
[9]
Wu X., Li J., Zhang L., Speight E., Rajamony R., Xie Y., Hybrid cache architecture with disparate memory technologies, Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 34-45, (2009)
[10]
Guo X., Ipek E., Soyata T., Resistive computation: Avoiding the power wall with low-leakage, stt-mram based computing, Proceedings of the 37th Annual International Symposium on Computer Architecture, ISCA '10, pp. 371-382, (2010)